The present invention relates to integrated circuits (IC) with multi-layer wiring, which are programmable by burning off fuses provided in advance for disconnecting specific circuitries such as redundancy circuitries to meet the specific requirements for each IC. More particularly, it relates to a method for fabricating an opening for each fuse formed in the IC, to release generated heat and for dispersing materials and bursting gas when the fuse is blown off.
Recently, there has been an increasing use of fuses such as polycrystalline silicon (polysilicon) fuses for permanently programmable circuit elements. For example, these are used for selecting redundant circuit blocks in MOS memories. As another example, they are used to provide an accurate reference voltage source for a D/A converter, a coder/decoder (CODEC) and so on, where the reference voltages are adjusted by trimming circuits with fuses arranged in the circuits. In both cases, the fuses are selectively blown off by electrical or laser power according to a predetermined programming method.
Generally, polysilicon fuses are currently in use because of their relatively higher resistivity as compared to other materials and the availability of IC fabrication processes. The fuses are blown off by passing high current according to predetermined programming data.
The polysilicon fuses are arranged generally on the silicon substrate and are formed together with other polysilicon conducting paths for wiring the desired circuit. They are arranged on the same layer together with other electronic components such as transistors, diodes, resistors, capacitors and the like. They are sandwiched by a substrate and insulating layers such as a silicon dioxide (SiO.sub.2) layer, a phospho-silicate glass (PSG) layer and so on, formed over the circuit layer to protect the circuit.
Usually a fuse is created by narrowing locally the width of the polysilicon conducting path at the portion where the fuse is to be positioned, so that the fuse will have higher resistivity than the remaining portion of the conducting path. By providing a specified electric current, the fuse (polysilicon resistor) is heated to a temperature high enough to be melted and blown off. Unfortunately, the generated heat at the fuse is conducted to the neighboring portions to heat them up to undesirable temperatures, which causes trouble. For example, the dopant concentration of an existing semiconductor junction might be changed. At the same time, the melted fuse material, and a vast volume of the gas released during the blowing off of the fuse, might burst out, thermally and mechanically destroying the layers in the vicinity of the fuse. This leads to disconnection or electrical shorting of the wiring and other damage. In addition, the blowing off is itself often not satisfactory and the circuitry of interest is not completely separated.
In order to eliminate these drawbacks, generally, an opening is arranged in a portion of any insulating layers over a fuse to expose the fuse to the surroundings, so as to dissipate the heat conducted from the blown off fuse and to release the dispersing melted material and gas. This is an effective countermeasure, but it is accompanied by another problem.
As the demand for higher integration increases, a multilayer wiring structure becomes applicable to these ICs. The multi-layer wiring system can provide the IC with not only a higher integration but also freedom of design for the IC. In the IC with a multi-layer wiring, a wiring layer must be covered by an insulating layer, and these are piled alternately until a necessary number of the wiring layers is completed. As a result, a fuse is covered by more than two insulating layers, and the openings must be formed by removing all the insulating layers over the fuse of interest. The removal of the insulating layers is performed by a conventional selective etching method, which is basically a chemical or physical process that is difficult to control for precise dimensions. This combines with a large thickness (more than several microns) of the insulator layers to be etched as described above, which causes difficulty in the process for fabricating the openings.
As an example, an IC device with two-layer wiring according to the prior art method will be described briefly. Enlarged, cross-sectional, elevation views are illustrated schematically in FIG. 1 and FIG. 2, showing the structure of the portion of a fuse before and after the etching operation for the opening respectively.
A silicon substrate 1 is covered by a silicon dioxide (SiO.sub.2) layer 2 on which a wiring layer 3 including a polysilicon resistor fuse 4 is formed. These are covered by a silicon dioxide (SiO.sub.2) layer 5 and a silicon nitride (Si.sub.3 N.sub.4) layer 6, over which a phosphosilicate glass (PSG) layer 7 is formed. The second wiring layer 8 (formed of aluminum) is formed on the first PSG layer 7 and is connected to the wiring layer 3 through a contact hole 10 opened in the layers 5, 6 and 7 by an etching method. Finally, a PSG layer 9 is formed over the second wiring layer 8 as a passivation layer. Then, a window 14 for a bonding pad 8a is opened in the PSG layer 9 by etching with the aid of photolithographic technology, over which a photoresist film 11 is formed. A window 12 is opened in this film 11 above the fuse 4. As shown in FIG. 1, the device is then ready for fabricating an opening.
As is clearly seen from the figure, in order to form an opening 13 over the fuse 4 to expose it to the air, it is necessary to etch through the whole thickness of layers 9, 7, 6 and 5. In such a case, the etching operation is done by a combination of chemical (wet) and physical (dry) etching operations, but a long etching time is necessary for this purpose, which results in problems such as unavoidable overetching and underetching (the respective portions are denoted by dotted areas 13x and 13y respectively in FIG. 2). As a result, in the case of an IC with multi-layer wiring, it is very difficult to provide the opening with accurately determined dimensions, or to avoid overetching of undesirable portions of the wiring layer. These lead to decreasing the fabrication yield of the IC device, and are serious disadvantages of the prior art methods.